If you survey hardware design groups, you will learn that between 60%
and 80% of their effort is dedicated to verification. This may seem
unusually large, but I include in "verification" all debugging and
correctness checking activities, not just writing and running
testbenches. Every time a hardware designer pulls up a waveform viewer,
he or she performs a verification task. With today's ASIC and FPGA sizes
and geometries, getting a design to fit and run at speed is no longer
the main challenge. It is to get the right design, working as intended,
at the right time. Unlike synthesizable coding, there is no particular
coding style nor language required for verification. The freedom of
using any l- guage that can be interfaced to a simulator and of using
any features of that language has produced a wide array of techniques
and approaches to verification. The continued absence of constraints and
historical shortage of available expertise in verification, c- pled with
an apparent under-appreciation of and under-investment in the
verification function, has resulted in several different ad hoc
approaches. The consequences of an informal, ill-equipped and
understaffed verification process can range from a non-functional design
requiring several re-spins, through a design with only a s- set of the
intended functionality, to a delayed product shipment.
