This book will help engineers write better Verilog/SystemVerilog design
and verification code as well as deliver digital designs to market more
quickly. It shows over 100 common coding mistakes that can be made with
the Verilog and SystemVerilog languages. Each example explains in detail
the symptoms of the error, the languages rules that cover the error, and
the correct coding style to avoid the error. The book helps digital
design and verification engineers to recognize, and avoid, these common
coding mistakes. Many of these errors are very subtle, and can
potentially cost hours or days of lost engineering time trying to find
and debug them. This book is unique because while there are many books
that teach the language, and a few that try to teach coding style, no
other book addresses how to recognize and avoid coding errors with these
languages.