This book targets custom IC designers who are encountering variation
issues in their designs, especially for modern process nodes at 45nm and
below, such as statistical process variations, environmental variations,
and layout effects. It teaches them the state-of-the-art in
Variation-Aware Design tools, which help the designer to analyze quickly
the variation effects, identify the problems, and fix the problems.
Furthermore, this book describes the algorithms and algorithm
behavior/performance/limitations, which is of use to designers
considering these tools, designers using these tools, CAD researchers,
and CAD managers.