Since process variation and chip performance uncertainties have become
more pronounced as technologies scale down into the nanometer regime,
accurate and efficient modeling or characterization of variations from
the device to the architecture level have become imperative for the
successful design of VLSI chips.
This book provides readers with tools for variation-aware design
methodologies and computer-aided design (CAD) of VLSI systems, in the
presence of process variations at the nanometer scale. It presents the
latest developments for modeling and analysis, with a focus on
statistical interconnect modeling, statistical parasitic extractions,
statistical full-chip leakage and dynamic power analysis considering
spatial correlations, statistical analysis and modeling for large global
interconnects and analog/mixed-signal circuits.
-
Provides readers with timely, systematic and comprehensive treatments
of statistical modeling and analysis of VLSI systems with a focus on
interconnects, on-chip power grids and clock networks, and
analog/mixed-signal circuits;
-
Helps chip designers understand the potential and limitations of their
design tools, improving their design productivity;
-
Presents analysis of each algorithm with practical applications in the
context of real circuit design;
-
Includes numerical examples for the quantitative analysis and
evaluation of algorithms presented.
-
Provides readers with timely, systematic and comprehensive treatments
of statistical modeling and analysis of VLSI systems with a focus on
interconnects, on-chip power grids and clock networks, and
analog/mixed-signal circuits;
-
Helps chip designers understand the potential and limitations of their
design tools, improving their design productivity;
-
Presents analysis of each algorithm with practical applications in the
context of real circuit design;
-
Includes numerical examples for the quantitative analysis and
evaluation of algorithms presented.
