Written by an acknowledged expert in the field, this book focuses on
approaches for designing secure hardware accelerators for digital signal
processing and image processing, which are also optimised for
performance and efficiency. State-of-the art security and optimization
algorithms are presented, and their roles in the design of secured
hardware accelerators for DSP, multimedia and image processing
applications are explored.
The book begins with an introduction to the principles of secured and
optimized hardware accelerators for DSP and image processing
applications. The following topics are then given thorough and
systematic coverage: cryptography driven IP steganography for DSP
hardware accelerators; double line of defence to secure JPEG codec
hardware for medical imaging systems; integrating multi-key based
structural obfuscation and low-level watermarking for double line of
defence of DSP hardware accelerators; multimodal hardware accelerators
for image processing filters; fingerprint biometric for securing
hardware accelerators; key-triggered hash-chaining based encoded
hardware steganography for Securing DSP hardware accelerators; designing
N-point DFT hardware accelerator using obfuscation and steganography;
and structural transformation and obfuscation frameworks for
data-intensive IPs.
Intended primarily for researchers and practicing engineers, the book
will also be of interest to graduate students with a particular interest
in hardware device security.
