Silicon technology now allows us to build chips consisting of tens of
millions of transistors. This technology not only promises new levels of
system integration onto a single chip, but also presents significant
challenges to the chip designer. As a result, many ASIC developers and
silicon vendors are re-examining their design methodologies, searching
for ways to make effective use of the huge numbers of gates now
available.
These designers see current design tools and methodologies as inadequate
for developing million-gate ASICs from scratch. There is considerable
pressure to keep design team size and design schedules constant even as
design complexities grow. Tools are not providing the productivity gains
required to keep pace with the increasing gate counts available from
deep submicron technology. Design reuse - the use of pre-designed and
pre-verified cores - is the most promising opportunity to bridge the gap
between available gate-count and designer productivity.
Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition
outlines an effective methodology for creating reusable designs for use
in a System-on-a-Chip (SoC) design methodology. Silicon and tool
technologies move so quickly that no single methodology can provide a
permanent solution to this highly dynamic problem. Instead, this manual
is an attempt to capture and incrementally improve on current best
practices in the industry, and to give a coherent, integrated view of
the design process. Reuse Methodology Manual for System-On-A-Chip
Designs, Second Edition will be updated on a regular basis as a result
of changing technology and improved insight into the problems of design
reuse and its role in producing high-quality SoC designs.
