Foreword. Preface. 1. INTRODUCTION. 1.1 Challenge: From Board to SoC.
1.2 Degrees of SoC Customization. 1.3 Organization of this Book. 2. SOC
DESIGN METHODOLOGIES. 2.1 Traditional HW/SW Co-Design. 2.2 System Level
Design. 2.3 Current Research on SoC Design Methodologies. 2.4
Contribution of this Work. 3. COMMUNICATION MODELING. 3.1 Transaction
Level Modeling. 3.2 Generic Communication Modeling. 3.3 Communication
Customization. 3.4 The BusCompiler Tool. 4. PROCESSOR MODELING. 4.1
Generic Processor Modeling. 4.2 Processor Customization Techniques. 4.3
LISA. 5. PROCESSOR SYSTEM INTEGRATION. 5.1 Simulator Structure. 5.2
Adaptors: Bridging Abstraction Gaps. 5.3 Commercial SoC Simulation
Environments. 6. SUCCESSIVE TOP-DOWN REFINEMENT FLOW. 6.1 Phase 1:
Standalone. 6.2 Phase 2: IA ASIP - AVF Communication Models. 6.3 Phase
3: IA ASIP - CA TLM Bus. 6.4 Phase 4: CA ASIP - CA TLM Bus. 6.5 Phase 5:
BCA ASIP - CA TLM Bus. 6.6 Phase 6: RTL ASIP - CA TLM Bus. 6.7 Phase 7:
RTL ASIP - RTL Bus. 7. AUTOMATIC RETARGETABILITY. 7.1 MP-SoC Simulator
Generation Chain. 7.2 Structure of the Generated Simulator. 7.3 Bus
Interface Specification. 8. DEBUGGING AND PROFILING. 8.1 Multiprocessor
Debugger. 8.2 TLM Bus Traffic Visualization. 8.3 Bus Interface Analysis.
9. CASE STUDY. 9.1 Multi Processor JPEG Decoding Platform. 9.2 Phase 2:
IA+AVF Platform. 9.3 Phase 3: IA + BusCompiler Platform. 9.4 Phase 4:
CA + BusCompiler Platform. 9.5 Phase 5: BCA + BusCompiler Platform. 10.
SUMMARY. Appendices. A. Businterface Definition Files. A.1 Generic AMBA
2.0 Protocol. A.2 Derived AMBA 2.0 Protocols. A.3 AMBA 2.0 Bus Interface
Specification. B. Extended CoWare Tool Flow. List of Figures.
References. Index.
