The book provides a comprehensive description and implementation
methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC).
The presentation offers a systems perspective, starting from the system
requirements and deriving and describing the resulting hardware
architectures, embedded software, and accompanying design flow. Readers
get an in depth view of the interconnect requirements, not centered only
on performance and scalability, but also the multi-faceted,
application-driven requirements, in particular composability and
predictability. The book shows how these qualitative requirements are
implemented in a state-of-the-art on-chip interconnect, and presents the
realistic, quantitative costs.