This book describes fault tolerance techniques based on software and
hardware to create hybrid techniques. They are able to reduce overall
performance degradation and increase error detection when associated
with applications implemented in embedded processors. Coverage begins
with an extensive discussion of the current state-of-the-art in fault
tolerance techniques. The authors then discuss the best trade-off
between software-based and hardware-based techniques and introduce novel
hybrid techniques. Proposed techniques increase existing fault detection
rates up to 100%, while maintaining low performance overheads in area
and application execution time.