High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip (Softcover Reprint of the Original 1st 2018)Paperback - Softcover Reprint of the Original 1st 2018, 12 May 2018

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.