The memory system is increasingly turning into a bottleneck in the
design of embedded systems. The speed improvements of memory systems are
lower than the speed improvements of processors, eventually leading to
embedded systems whose performance is limited by the memory. This
problem is known as the "memory wall" problem. Furthermore, memory
systems may consume the largest share of the system's energy budget and
may be the source of unpredictable timing behaviour. Hence, the design
of the memory system deserves an increasing amount of attention.
Fast, Efficient and Predictable Memory Accesses presents techniques
for designing fast, energy-efficient and timing predictable memory
systems. By using a careful combination of compiler optimizations and
architectural improvements, we can achieve more than what would be
feasible at one of the levels in isolation. The described optimization
algorithms achieve the goals of high performance and low energy
consumption. In addition to these benefits, the use of scratchpad
memories significantly improves the timing predictability of the entire
system, leading to tighter worst case execution time bounds (WCET). The
WCET is a relevant design parameter for all timing critical systems. In
addition, the book covers algorithms to exploit the power down modes of
main memories in SDRAM technology, as well as the execute-in-place
feature of Flash memories. The final chapter considers the impact of the
register file, which is also part of the memory hierarchy.
