Voltage-controlled oscillators (VCOs) with low phase noise are the most
critical building block in high performance phase-locked loops (PLL).
Design of High-Performance CMOS Voltage-Controlled Oscillators
presents a phase noise modeling framework for CMOS ring oscillators. The
analysis considers both linear and nonlinear operation. It indicates
that fast rail-to-rail switching has to be achieved to minimize phase
noise. Additionally, in conventional design the flicker noise in the
bias circuit can potentially dominate the phase noise at low offset
frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion
for the bias circuits should be minimized. We define the effective Q
factor (Qeff) for ring oscillators and predict its increase for CMOS
processes with smaller feature sizes. Our phase noise analysis is
validated via simulation and measurement results.
The digital switching noise coupled through the power supply and
substrate is usually the dominant source of clock jitter. Improving the
supply and substrate noise immunity of a PLL is a challenging job in
hostile environments such as a microprocessor chip where millions of
digital gates are present. Design of High-Performance CMOS
Voltage-Controlled Oscillators noise, analyzes the impact of the
supply and substrate noise on the oscillator phase noise, and suggests
techniques for reducing the jitter due to the supply and substrate
noise.
The primary audience for Design of High-Performance CMOS
Voltage-Controlled Oscillators is research workers and design engineers
who concentrate on high performance communication circuits. This work
will also be of interest to analog circuit designers.
