Vaibbhav Taraate

(Author)

ASIC Design and Synthesis: Rtl Design Using Verilog (2021)Hardcover - 2021, 7 January 2021

ASIC Design and Synthesis: Rtl Design Using Verilog (2021)
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Print Length
330 pages
Language
English
Publisher
Springer
Date Published
7 Jan 2021
ISBN-10
9813346418
ISBN-13
9789813346413

Description

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Product Details

Author:
Vaibbhav Taraate
Book Edition:
2021
Book Format:
Hardcover
Country of Origin:
NL
Date Published:
7 January 2021
Dimensions:
23.39 x 15.6 x 2.06 cm
ISBN-10:
9813346418
ISBN-13:
9789813346413
Language:
English
Location:
Singapore
Pages:
330
Publisher:
Weight:
671.32 gm

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