The prospect of initializing a network-ubiquitous society in the years
to come has led to the development of multistandard-compliant wireless
transceivers for seamless roaming among multiple networks. To ensure a
commercial success of such a development, the manufacturing cost and
power consumption of the system chips have to be minimized. The use of
an advanced technology and a high level of integration have continued to
be the most effective ways for cost and power minimization, given that
wireless chips integrate large amounts of digital logic for computation.
Regrettably, entering into the nanoelectronics era, the thinner
transistor gate oxide implicates great challenges in the design of the
analog front-ends. While a low-voltage supply is imposed to maintain
device reliability, a relatively large threshold voltage is also
necessitated to limit the leakage current. Thus, transceiver
architectures and circuits which will befit future full integration of
multistandard wireless transceivers in sub-1V nanoscale CMOS processes
must be highly reconfigurable and robustly operational underneath a l-
voltage supply. This book presents novel analog-baseband architectures
and circuits that help realizing multistandard and low-voltage wireless
transceivers. The main contents are presented from Chapter 2 to Chapter
6, as pictorially outlined in Figure 1. Chapter 1 overviews the current
wireless-IC developments and presents the motivation and research
objectives of this book. xi xii Preface Figure 1.
