Vaibbhav Taraate

(Author)

Advanced Hdl Synthesis and Soc Prototyping: Rtl Design Using Verilog (2019)Hardcover - 2019, 18 January 2019

Advanced Hdl Synthesis and Soc Prototyping: Rtl Design Using Verilog (2019)
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Print Length
307 pages
Language
English
Publisher
Springer
Date Published
18 Jan 2019
ISBN-10
981108775X
ISBN-13
9789811087752

Description

Explains SOC architecture and micro-architecture design with case studies

Covers practical scenarios and issues, helpful to both students and professionals

Discusses systems design and testing scenarios using modern FPGAs

Product Details

Author:
Vaibbhav Taraate
Book Edition:
2019
Book Format:
Hardcover
Country of Origin:
NL
Date Published:
18 January 2019
Dimensions:
23.39 x 15.6 x 1.91 cm
ISBN-10:
981108775X
ISBN-13:
9789811087752
Language:
English
Location:
Singapore
Pages:
307
Publisher:
Weight:
639.56 gm

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