This book helps readers create good VHDL descriptions and simulate VHDL
designs. It teaches VHDL using selected sample problems, which are
solved step by step and with precise explanations, so that readers get a
clear idea of what a good VHDL code should look like.
The book is divided into eight chapters, covering aspects ranging from
the very basics of VHDL syntax and the module concept, to VHDL logic
circuit implementations. In the first chapter, the entity and
architecture parts of a VHDL program are explained in detail. The second
chapter explains the implementations of combinational logic circuits in
VHDL language, while the following chapters offer information on the
simulation of VHDL programs and demonstrate how to define data types
other than the standard ones available in VHDL libraries. In turn, the
fifth chapter explains the implementation of clocked sequential logic
circuits, and the sixth shows the implementation of registers and
counter packages. The book's last two chapters detail how components,
functions and procedures, as well as floating-point numbers, are
implemented in VHDL.
The book offers extensive exercises at the end of each chapter, inviting
readers to learn VHDL by doing it and writing good code.